Category: base24

eBUG (European BASE24 User Group) Conference Overview and Chronological  Timeline

The eBUG (European BASE24 User Group) Conference is the premier annual gathering for financial institutions, retail banking professionals, and technical architects utilizing ⁠ACI Worldwide’s foundational retail payment engine, BASE24 and BASE24-eps.

Operating alongside global HPE NonStop hardware environments, the conference traditionally functions as a collaborative technical focus group (TFG) and customer roundtable. It brings together industry experts to address mission-critical transaction switching, regulatory compliance mandates, payment security architectures, and core software migrations.

Detailed Era Breakdown & Timeline

Era 1: The Classic BASE24 & ITUG Tandem Era (1980s – Late 1990s)

Focus: Evolution of core ATM/POS switching on Tandem (HPE NonStop) platforms, localized compliance, and basic card processing networks.

  • 1982–1985: The birth of the early European user networks following the launch of BASE24 software by Applied Communications Inc. (now ACI Worldwide). Early meetings are heavily dependent on regional vendor user group support.
  • 1992: Initial formations of explicit regional sub-committees under the International Tandem User Group (ITUG). The European base of users establishes formal communication pipelines.
  • 1996: Increased focus on the early adoption of regional card mandates, standardising early transaction switching over X.25 networks, and prepping mainframe systems for high-availability roundups.
  • 1999: A definitive milestone focused on Y2K compliance readiness. Conferences during this era are heavily centered on stress-testing legacy BASE24 code blocks, ensuring clock dates rollover flawlessly across financial networks without disrupting global merchant processing.

Era 2: The EMV Mandate & “Classic-to-EPS” Transition Era (2000 – 2010)

Focus: Overhauling core code for Chip & PIN (EMV) regulations, migrating toward open system frameworks, and introducing the next-generation BASE24-eps payment platform.

  • 2003: The EMV Blueprint Era. The conference takes a primary steering role for European banks facing strict Eurocard, Mastercard, and Visa (EMV) liabilities. User sessions heavily focus on updating terminal messaging scripts.
  • 2005: Introduction of BASE24-eps to the wider user group community. Discussions shift away from the classic architecture toward modern open-systems deployments, leveraging UNIX, Linux, and IBM z/OS alongside traditional NonStop environments.
  • 2007 (Istanbul, Turkey): The group expands geographic footprints into the borders of Europe and Asia. Themes heavily stress global interoperability, cross-border transactional routing, and real-time fraud monitoring.
  • 2008 (Vienna, Austria): High-water mark for attendance during the mid-2000s. Presentations focus on deep-dive technical configurations of BASE24-eps Release 08.2, service-oriented architecture (SOA) wrappers, and high-availability testing matrices.
  • 2009 (Prague, Czech Republic): Real-time monitoring tools become a central talking point. Despite global financial pressures, the user community explicitly defends the strength of ⁠HPE NonStop infrastructure for running foundational retail networks.

Era 3: Security Hardening & The Independent Pivot Era (2011 – 2018)

Focus: Adapting payment loops to rigid PCI-DSS requirements, cloud capability tracking, and shifting the conference structure to independent consulting sponsorships.

  • 2011: Focus turns squarely onto PCI-DSS Compliance and tokenisation. Roundtables detail architectural techniques to secure transaction journals, encrypt key lines, and prevent man-in-the-middle exploits at the ATM level.
  • 2012 (London, UK): Held at the historic ⁠Trinity House near Tower Bridge, this event marks a structural pivot. Moving away from a pure ACI-hosted workspace, independent payment consultancies (such as PayX) drive user discussions. This Technical Focus Group explicitly evaluates the limits of legacy systems against “intelligent” multi-vendor ATM software.
  • 2015: Immediate focus addresses the challenges of Real-Time / Instant Payments mandates across the Eurozone. Systems engineers share optimization scripting paradigms to support sub-second processing SLA ceilings.
  • 2018: The rise of Open Banking / PSD2 Regulations. Technical breakout sessions outline how to safely open classic BASE24 architectures to third-party APIs through microservices wrappers and middleware adapters without breaking strict system uptime criteria.

Era 4: Modernisation & Cloud-Native Coexistence Era (2019 – Present)

Focus: ISO 20022 message standard migrations, cloud-native deployments, and containerization strategies.

  • 2020–2022: Transition to hybrid tracking methodologies due to travel constraints. The baseline focus targets data integration, remote system management, and virtualized system-hardening techniques.
  • 2023–2024: The ISO 20022 Mandate. Sessions are dominated by the industry-wide migration from legacy ISO 8583 message lines to the XML-based ISO 20022 financial standard. Systems architects present automated script parsers to translate real-time payment formats across legacy logic systems.
  • 2025–2026: Integration of ⁠Cloud-Native BASE24-eps architectures. Contemporary meetups explore containerized execution patterns, utilizing AI models within the authorization loop to spot edge-case fraud patterns in real-time, and evaluating long-term roadmaps for hardware-security modules (HSMs).

eBUG (European BASE24 User Group) Conference Overview and Chronological  Timeline

Connect – HPE NonStop Technology & Business Conference, Nonstop TBC, 2026

The HPE NonStop Technology & Business Conference (Nonstop TBC 2026)—hosted by Connect Worldwide—will take place from September 14 to September 17, 2026, at The Rosen Plaza in Orlando, Florida.

The HPE NonStop Technology & Business Conference (Nonstop TBC 2026)—hosted by Connect Worldwide—will take place from September 14 to September 17, 2026, at The Rosen Plaza in Orlando, Florida
Connect – HPE NonStop Technology &
Business Conference (Nonstop TBC 2026)

This signature annual event brings together enterprise IT leaders, software engineers, and solution architects to explore innovations shaping mission-critical environments.

Core Event Schedule

The four-day conference partitions its educational and collaborative tracks as follows:

  • September 14: Dedicated exclusively to HPE Education Day, featuring expanded deep-dive technical pre-conference courses.
  • September 15–17: The primary conference technical program and breakout sessions.

Key Focus Areas & Tracks

The 2026 event focuses heavily on bridging mission-critical legacy stability with modern software frameworks:

  • AI-Driven Transformation: Adapting continuous availability to the demands of modern artificial intelligence and machine learning workloads.
  • Digital Resilience & Security: Mitigating modern risks, modernising backup systems, and maintaining absolute runtime security.
  • FinTech & Payments: Real-world operational strategies from global peers managing transaction-heavy workloads.
  • Expanded Business Track: New for 2026, this track aligns executive business drivers with technical architectures for practical IT roadmap building.

Logistics and Pricing

  • Venue: The Rosen Plaza Hotel, situated at 9700 International Drive, Orlando, Florida.
  • Pricing: A newly reduced Early Bird Registration ticket is available for $895.
  • Accommodations: Registered attendees gain access to a dedicated Connect block rate of $181 per night (including tax).
  • Sponsorships: Major industry partners, such as comforte, sponsor the event, granting enterprise buyers direct visibility into third-party NonStop infrastructure add-ons.

Connect Worldwide – HPE NonStop Technology & Business Conference, Nonstop TBC, 2026

HPE NonStop architecture (Tandem Computers) by Era and Year

Mark Whitfield invested many years in the HPE NonStop field from 1990. The HPE NonStop architecture (originally Tandem Computers) is a legendary fault-tolerant system known for 100% continuous availability. The platform’s hardware and software execution evolved across six distinct eras and processor transitions:

1. The Tandem Founding Era (1976–1981)

  • Years: 1976–1981
  • Processors: Proprietary 16-bit stack processors (e.g., Tandem/16, NonStop II)
  • Architecture: The foundational “shared-nothing” parallel architecture. Featured redundant components (processors, disks, power supplies) connected by a proprietary dual-bus (Dynabus). The operating system provided instant automated failover.

2. The Cyclone & Early RISC Era (1981–1996)

  • Years: 1981–1996
  • Processors: Proprietary non-RISC (NonStop Cyclone) & MIPS R-series RISC
  • Architecture: Expanded into 32-bit computing. To keep pace with industry performance, Tandem transitioned from proprietary processors to off-the-shelf MIPS RISC processors while heavily emulating the original instruction set for compatibility.

3. The Himalaya/ServerNet Era (1997–2004)

  • Years: 1997–2004
  • Processors: MIPS R-series
  • Architecture: Replaced the legacy Dynabus with ServerNet, a high-speed system interconnect that served as an early precursor to modern networking fabrics. (Compaq acquired Tandem in 1997, which subsequently merged with HP in 2002).

4. The Integrity Itanium Era (2005–2013)

  • Years: 2005–2013
  • Processors: Intel Itanium (TNS/E)
  • Architecture: Branded as HP Integrity NonStop (NonStop i). The platform moved off proprietary silicon to standard Intel Itanium processors. This was driven by the “NonStop Advanced Architecture” (NSAA), lowering hardware costs while maintaining Availability Level 4 (AL4) standards.

5. The NonStop X (x86-64) Era (2014–Present)

  • Years: 2014–2026
  • Processors: Intel Xeon x86-64 (TNS/X)
  • Architecture: Fully decoupled the OS from proprietary hardware by shifting to standard Intel x86-64 processors and InfiniBand fabric. The latest compute nodes (such as the NS5 X5 and NS9 X5) utilize modern Intel Xeon Scalable processors to maintain maximum Availability Level 4 (AL4) workloads.

6. The Virtualized NonStop Era (Present)

  • Years: 2015–Present
  • Processors: Virtual Machines / Cloud / x86
  • Architecture: HPE extended the platform to support Virtualized NonStop Software, allowing fault-tolerant enterprise workloads to run entirely in private clouds via standard VMware or hybrid architectures, independent of specific physical servers.
Globally published HP NonStop journal – ‘The Connection’
HPE NonStop article by Mark Whitfield in 2013, working for Insider Technologies Limited in Salford Quays

BASE24 and BASE24-eps architecture overview

The BASE24 electronic payment system developed by ACI Worldwide exists in two primary architectural generations:

BASE24 Classic (historically deployed on HPE NonStop / Tandem fault-tolerant hardware) and

BASE24-eps (Enterprise Payments System, built using an object-oriented C++ framework deployable across open systems, z/OS, and cloud infrastructure).

Despite structural differences, both share a highly optimized, component-based transaction routing engine.

BASE24 and BASE24-eps architecture overview
BASE24 architecture overview

Core Structural Component Layers

The component architecture maps the complete end-to-end lifecycle of a financial message (such as ISO 8583) through five distinct functional sub-systems:

1. Network & Message Routing Component (XPNET)

  • Purpose: Coordinates all message traffic across internal processes and physical network nodes.
  • Function: Operates as a specialized middleware network manager that decouples low-level communication links from upper transaction routing layers.
  • Configuration: Relies on a Logical Network Configuration File (LCONF) to define active execution nodes, hardware lines, and physical stations.

2. Perimeter Access Layer (Device Handlers)

  • Purpose: Translates device-specific message protocol formats into the system’s unified internal format.
  • ATM Device Handlers (ATMDH): Manage direct connectivity to automated teller machines, unpack specific vendor dialects (such as Diebold or NCR states), and track terminal hardware statuses.
  • POS Device Handlers (POSDH): Interface with point-of-sale acquirer terminals and merchants.
  • Security Operations: Triggers immediate payload encryption/decryption and Hardware Security Module (HSM) PIN-block translation directly within this ingestion ring.

3. Core Transaction Logic (Authorization System)

  • Purpose: Determines whether a payment request should be accepted, rejected, or modified.
  • Full On-Us Authorization: Inspects internal databases for matching account records, positive balances, and velocity thresholds to issue real-time decisions.
  • Parametric/Negative Checks: Validates card status against offline negative files, usage restrictions, or custom risk parameters.
  • Scripting Engine: Modern BASE24-eps variants execute localized transaction routing scripts via customized operators without forcing a compile rewrite of the core engine core.

4. Boundary Channels (Interchange & Host Interfaces)

  • Interchange Interfaces (ICH): Package and transform the transaction payload into international network profiles (e.g., Visa, Mastercard, regional switches). It handles strict message mapping and regional network check requirements.
  • Host Interfaces (HIF): Create synchronous links back to an institution’s underlying Core Banking system to apply ledger adjustments, check balances, or execute real-time holds.

5. Offline & Administrative Subsystems

  • Extract Component: Gathers active transaction logs and streams filtered payloads out to analytical reporting databases.
  • Refresh Component: Updates terminal operational data, key packages, and card exclusion lists from parent systems down to active execution nodes.
  • Settlement Initiator: Groups, cleanses, and batches net-clearing totals to finalize payment entries into regional clearinghouses.

Architectural Divergence: Classic vs. EPS

The structural design varies significantly depending on the generation of the software deployment:

BASE24 and BASE24-eps architecture overview
BASE24 and BASE24-eps architecture overview

End-to-End Component Transaction Flow

  1. An ATM transaction arrives at the network interface layer managed by XPNET.
  2. The message is routed to the Device Handler, which strips hardware packaging and requests translation from the HSM.
  3. The clean internal message passes to the Authorization Engine.
  4. If it is a “Not-On-Us” card, the engine identifies the destination BIN and transfers routing control to the Interchange Interface.
  5. The Interchange Interface maps the payload to the external scheme standard (such as Visa) and transmits it to the external network.
  6. The outbound network response is unwrapped by the Interchange component and tracked through the core engine to log final response codes.
  7. The transaction safely records inside the active log file, allowing the Extract / Settlement components to pick it up later during batch processing.

BASE24 and BASE24-eps architecture overview

BASE24 and BASE24-eps architecture overview
BASE24 and BASE24-eps architecture overview