The Software Partnership was a highly specialized software house in Runcorn

The Software Partnership (TSP) was a highly specialized British software house based in Runcorn, Cheshire, that played a key role in early cutting-edge electronic banking software. The firm famously developed sp/ARCHITECT-BANK, an innovative enterprise banking system built explicitly for Tandem Computers (now HPE NonStop) fault-tolerant server systems. I was based there between 1990 and 1995.

The Software Partnership Logo, Runcorn Software House, Deluxe Data
The Software Partnership Logo

Below is a detailed overview of the company’s operational history, alongside the corresponding hardware/software architectural eras of the HPE NonStop platform it relied upon.


Detailed Overview

  • Core Focus: The Software Partnership specialized in online transaction processing (OLTP) and electronic automated banking software. Long before the internet became mainstream, TSP engineered early desktop access environments for corporate bookkeeping and inter-account bank transfers.
  • Key Product: Its flagship software suite, sp/ARCHITECT, ran on Tandem’s highly unique, redundant architecture. The software handled complex high-volume retail transactions, ATM networking, and ledger balances.
  • Major Clients: High-profile financial institutions deployed TSP’s systems, including TSB (Trustee Savings Bank), Bank of Scotland, Rabobank, and Denmark’s Girofon.
  • Legacy: TSP initiated a massive lineage of financial tech operations in the Runcorn/Warrington area. After subsequent buyouts and transitions, its corporate DNA integrated into modern banking giants, eventually operating under Fidelity National Information Services (FIS).

Detailed Timeline by Era and Year

The history of TSP mirrors the evolution of the underlying fault-tolerant architecture originally built by Tandem, later managed by Compaq, HP, and currently Hewlett Packard Enterprise (HPE).

Era 1: The Tandem Founding & TSP Inception (Mid-1970s – 1989)

This era is marked by Tandem’s creation of the fault-tolerant server market, which birthed the niche that TSP filled.

  • 1974–1976: Tandem Computers is founded and ships its first 16-bit NonStop I (T/16) system, utilizing complete component redundancy to guarantee close to zero downtime for the financial industry.
  • 1981: Tandem introduces the NonStop II, transitioning to battery-backed DRAM memory and enabling early 32-bit addressing.
  • Mid-1980s: The Software Partnership (TSP) is co-founded by Nigel Walsh. It establishes offices first in Timperley (Wingate Drive), then moves to Crowngate (Norton House) in Runcorn. The team begins developing online banking architectures explicitly for Tandem OS (Guardian) and early UNIX nodes.
  • 1989: Tandem launches the NonStop Cyclone, a high-end mainframe system featuring superscalar CPUs and fiber-optic interconnects.

Era 2: The MIPS RISC Transition & Corporate Buyouts (1990 – 1999)

TSP reaches peak software deployment exactly as Tandem shifts its internal processor technology.

  • 1990: TSP establishes itself as a major regional employment hub for software engineers following a massive boom in terminal banking technology. Software programmers deploy sp/ARCHITECT-BANK code for massive retail banks internationally.
  • 1991: Tandem shifts its structural hardware away from proprietary chips, introducing its first MIPS RISC-based NonStop systems.
  • 1992: TSP expands its Runcorn footprint, moving to custom facilities at Wingate House on Northway, Runcorn.
  • 1994: TSP is acquired by American firm Deluxe Electronic Payment Systems (a division of Deluxe Corporation, one of the largest check printers and transaction processors in the US). The corporate name transitions to Deluxe Data.
  • 1997: Due to shifts in the enterprise hardware landscape, Compaq Computer Corporation acquires Tandem Computers for $3 billion, taking over the NonStop lineage.

Era 3: The Itanium Migration & eFunds Realignment (2000 – 2013)

The architecture sheds its proprietary processors for industry standards, and TSP’s corporate legacy transforms.

  • 2000: Deluxe Data’s electronic payment wing splits off and rebrands as EFD eFunds.
  • 2001–2002: HP (Hewlett-Packard) merges with Compaq, absorbing the NonStop portfolio. Simultaneously, HP begins shifting NonStop servers from MIPS architectures to Intel Itanium processors.
  • 2007: Following industry consolidation, the corporate remnants of the original TSP Runcorn operations are absorbed into Fidelity National Information Services (FIS) and relocated to Aegon House in Daresbury, Warrington.

Era 4: The Modern HPE NonStop X & Virtualization Era (2014 – Present)

The legacy of the high-availability software pioneered in Runcorn culminates in cloud and x86 integration.

  • 2014: HP introduces NonStop X, completely migrating the underlying architecture to Intel x86-64 processors and implementing InfiniBand connectivity fabrics.
  • 2015: Hewlett-Packard officially splits into two entities; the core mission-critical banking platform continues its five-decade lineage under Hewlett Packard Enterprise (HPE).
  • 2020s–Present: HPE modernizes the software architecture to support Virtualized NonStop Software (vNS). Modern variants allow banking systems to run mission-critical apps seamlessly inside enterprise private clouds and scalable HPE GreenLake consumption models with 100% fault tolerance.
Deluxe Data International Operations, Wingate House, Northway, Runcorn, Cheshire
Deluxe Data International Operations, Wingate House, Northway, Runcorn, Cheshire
The Software Partnership, Norton House, Crowngate, Runcorn, Cheshire
The Software Partnership, Norton House, Crowngate, Runcorn, Cheshire

⚙️ sp/ARCHITECT

sp/ARCHITECT (specifically sp/ARCHITECT-BANK) was a foundational electronic banking and transaction framework engineered in the 1990s by The Software Partnership (a UK-based fintech house later acquired by Deluxe Data). It primarily powered corporate banking portals and telephone-driven banking services.

The platform acted as highly reliable middleware, serving as a bridge between the customer and back-end banking mainframes. The breakdown of its architecture, infrastructure, and core functions includes:

⚙️ Architectural Breakdown

  • Hardware & OS: Built to run natively on fault-tolerant Tandem NonStop computers (now HPE NonStop). This “shared-nothing” architecture was designed for absolute transactional uptime and zero data loss.
  • Programming Languages: Built using legacy enterprise standards. Code was primarily written in COBOL85 and TAL (Transaction Application Language) native to the Tandem ecosystem.
  • Middleware Integration: Utilized Tandem-specific middleware like Pathway and Remote Server Call (RSC) to handle client-to-host communications.

💻 Core Capabilities & Modules

  • Electronic Delivery Framework: Served as a multi-channel framework, accommodating a wide variety of early access devices like desktop clients, UNIX workstations, and smart phones.
  • Transaction Handlers: Deployed custom scripts/handlers that enabled end-users to securely access real-time account data and perform early inter-account transfers without visiting a physical branch.
  • Testing Utilities: Included proprietary simulation tools like sp/TESTBED, acting as a PC-to-host test harness so developers could emulate user queries and transaction flows.

🏦 Industry Footprint

  • European Rollout: Heavily adopted by large European financial institutions, including TSB, Rabobank, Bank of Scotland, and Girofon.
  • BBM II Integration: Powered landmark corporate desktop banking solutions like Barclays Business Master II (BBM II), long before modern web browser banking existed.
  • Evolution: Following its acquisition, its design philosophies eventually evolved into Deluxe Data’s broader CONNEX suite of payment solutions.

HPE NonStop architecture (Tandem Computers) by Era and Year

Mark Whitfield invested many years in the HPE NonStop field from 1990. The HPE NonStop architecture (originally Tandem Computers) is a legendary fault-tolerant system known for 100% continuous availability. The platform’s hardware and software execution evolved across six distinct eras and processor transitions:

1. The Tandem Founding Era (1976–1981)

  • Years: 1976–1981
  • Processors: Proprietary 16-bit stack processors (e.g., Tandem/16, NonStop II)
  • Architecture: The foundational “shared-nothing” parallel architecture. Featured redundant components (processors, disks, power supplies) connected by a proprietary dual-bus (Dynabus). The operating system provided instant automated failover.

2. The Cyclone & Early RISC Era (1981–1996)

  • Years: 1981–1996
  • Processors: Proprietary non-RISC (NonStop Cyclone) & MIPS R-series RISC
  • Architecture: Expanded into 32-bit computing. To keep pace with industry performance, Tandem transitioned from proprietary processors to off-the-shelf MIPS RISC processors while heavily emulating the original instruction set for compatibility.

3. The Himalaya/ServerNet Era (1997–2004)

  • Years: 1997–2004
  • Processors: MIPS R-series
  • Architecture: Replaced the legacy Dynabus with ServerNet, a high-speed system interconnect that served as an early precursor to modern networking fabrics. (Compaq acquired Tandem in 1997, which subsequently merged with HP in 2002).

4. The Integrity Itanium Era (2005–2013)

  • Years: 2005–2013
  • Processors: Intel Itanium (TNS/E)
  • Architecture: Branded as HP Integrity NonStop (NonStop i). The platform moved off proprietary silicon to standard Intel Itanium processors. This was driven by the “NonStop Advanced Architecture” (NSAA), lowering hardware costs while maintaining Availability Level 4 (AL4) standards.

5. The NonStop X (x86-64) Era (2014–Present)

  • Years: 2014–2026
  • Processors: Intel Xeon x86-64 (TNS/X)
  • Architecture: Fully decoupled the OS from proprietary hardware by shifting to standard Intel x86-64 processors and InfiniBand fabric. The latest compute nodes (such as the NS5 X5 and NS9 X5) utilize modern Intel Xeon Scalable processors to maintain maximum Availability Level 4 (AL4) workloads.

6. The Virtualized NonStop Era (Present)

  • Years: 2015–Present
  • Processors: Virtual Machines / Cloud / x86
  • Architecture: HPE extended the platform to support Virtualized NonStop Software, allowing fault-tolerant enterprise workloads to run entirely in private clouds via standard VMware or hybrid architectures, independent of specific physical servers.
HPE NonStop article by Mark Whitfield in 2013, working for Insider Technologies Limited in Salford Quays

Barclays Business Master II (BBM II), Tandem Computers (HPE NonStop) & sp/ARCHITECT

These terms map directly to the foundational 1990s technology stack behind Barclays Business Master II (BBM II), one of the UK’s earliest enterprise electronic desktop banking platforms.

Before the mainstream internet, this corporate banking infrastructure relied on specialized high-availability mainframe software to process secure corporate transactions.

🧱 Architectural Component Breakdown

  • Barclays Business Master (BBM / BBM II): A landmark corporate desktop electronic banking solution developed by Barclays Bank. It allowed businesses to dial directly into the bank to perform inter-account transfers, check balances, and automate book-keeping long before web browser banking became standard.
  • sp/ARCHITECT (or sp/ARCHITECT-BANK): The core electronic banking software package that powered BBM. It was originally engineered in the late 1980s and early 1990s by The Software Partnership (a UK-based fintech software house based in Runcorn that was later acquired by Deluxe Data). It eventually evolved into the widely known CONNEX advantage payment solution.
  • NonStop (Tandem Computers): The underlying hardware and operating system environment. Because banking infrastructure requires absolute uptime, sp/ARCHITECT was built to run on Tandem NonStop fault-tolerant computers (now HPE NonStop). These systems utilize a unique “shared-nothing” architecture to ensure zero transactional data loss.

💻 Legacy Technical Environment

During the era when BBM was deployed across Barclays’ tech hubs (such as Knutsford), developers working on this specific stack utilized highly specialized mainframe tools:

  • Languages: Code for sp/ARCHITECT was primarily written in TAL (Transaction Application Language) or COBOL85, which were native to the Tandem platform.
  • Interfaces: Early implementations integrated desktop client interactions with the Tandem host via middleware components like Tandem Pathway and Remote Server Call (RSC) facilities.

Barclays Business Master II (BBM II), Tandem Computers (HPE NonStop) & sp/ARCHITECT

I was assigned by Deluxe Data (International Operations), to the BBM II project between 1992 – 93.

mark whitfield thesoftwarepartnershipwingatehousenorthwaysmall

Deluxe Data, Wingate House, Northway, Runcorn

HPE NonStop System Monitoring Reflex Product

HPE NonStop Reflex (often referred to as Reflex 80:20) is a graphical, integrated IT management suite developed by Insider Technologies. It provides continuous health monitoring, automated workflow management, and diagnostic logging for mission-critical HPE NonStop environments, serving as a single, consolidated “pane of glass” for fault-tolerant network operations.

Detailed Timeline Breakdown by Era & Year

The history of the NonStop Reflex suite closely mirrors the architectural evolution of the underlying HPE NonStop (originally Tandem) fault-tolerant hardware platforms.

1. The Tandem / ITUG Era (1989 – 1996)

  • 1989: Insider Technologies was founded in Salford Quays, Manchester, UK, establishing an early specialization in Tandem (NonStop) messaging software and message tracking utilities.
  • 1990s: As massive online transaction processing (OLTP) workloads grew, native Tandem utilities proved increasingly cumbersome. This spurred the initial development of platform diagnostic and event-filtering tools that would soon become the Reflex suite.
  • 1995: Insider Technologies actively codes and launches the initial iterations of Reflex 80:20, providing operators with an aggregated view of Tandem platform events.

2. The Compaq & Early HP Transition Era (1997 – 2014)

  • 1997: Compaq acquires Tandem Computers. Reflex 80:20 begins updating its backend architecture to handle ServerNet clustering and the newly combined enterprise platforms.
  • 2002: Hewlett-Packard (HP) acquires Compaq. HP begins the hardware migration from proprietary processors to Intel Itanium (HP Integrity NonStop).
  • 2004: Insider Technologies formalizes its ongoing product development, heavily pushing both Reflex 80:20 and releasing new variants like Reflex ONE24 to support extended tracking for ATM and POS networks.
  • 2007: Reflex and other Insider monitoring software platforms are highly integrated into FIS solutions, serving tier-one global banks and stock exchanges.
  • 2013: Insider Technologies solidifies the Reflex 80:20 status as the ultimate consolidated replacement for legacy HP components, publishing technical insights in dedicated NonStop journals.

3. The Modern HPE & x86 Era (2014 – 2019)

  • 2014: Hewlett Packard Enterprise (HPE) is formed and officially launches NonStop X, moving the architecture onto standard Intel x86-64 processors. Reflex 80:20 interfaces are updated to support InfiniBand fabrics and the newer Open System Services (OSS) environments.
  • 2017 – 2019: HPE launches Virtualized NonStop (vNS), bringing continuous application fault tolerance directly to private and hybrid clouds. Reflex adapts its system management capabilities to securely monitor both physical x86 non-stop servers and virtual hypervisor instances.

4. The AI & Hybrid Cloud Era (2020 – 2026)

  • 2020: HPE ends the sale of older Itanium-based platforms. Reflex fully commits its diagnostic support to modern HPE NonStop X and vNS environments.
  • 2023 – 2024: The NonStop platform embraces AI integrations, expanded SQL/cloud workloads, and integrations with modern DevOps tools. Reflex tools receive updates to accommodate enhanced cyber resilience tracking and modern API-driven services.
  • 2025: HPE celebrates 50 years of the fault-tolerant NonStop computing ecosystem. The Reflex suite provides compatibility for the upgraded, high-capacity hardware iterations running the L25 series OS.
  • 2026: Reflex remains a staple ecosystem management suite for complex enterprise networks, processing and escalating exception conditions, EMS events, and subsystem alerts within the highly available HPE GreenLake consumption models.

The Insider RTLX product at ETI-NET is now called C-Deep for Transaction Monitoring;

C-Deep (Transaction Monitoring)

The Insider Reflex product at ETI-NET is now called Sentinel for NonStop Monitoring;

Sentinel (Nonstop Monitoring)

C-Deep for Transaction Monitoring & Sentinel for HPE NonStop Monitoring

BASE24 and BASE24-eps architecture overview

The BASE24 electronic payment system developed by ACI Worldwide exists in two primary architectural generations:

BASE24 Classic (historically deployed on HPE NonStop / Tandem fault-tolerant hardware) and

BASE24-eps (Enterprise Payments System, built using an object-oriented C++ framework deployable across open systems, z/OS, and cloud infrastructure).

Despite structural differences, both share a highly optimized, component-based transaction routing engine.

BASE24 and BASE24-eps architecture overview
BASE24 architecture overview

Core Structural Component Layers

The component architecture maps the complete end-to-end lifecycle of a financial message (such as ISO 8583) through five distinct functional sub-systems:

1. Network & Message Routing Component (XPNET)

  • Purpose: Coordinates all message traffic across internal processes and physical network nodes.
  • Function: Operates as a specialized middleware network manager that decouples low-level communication links from upper transaction routing layers.
  • Configuration: Relies on a Logical Network Configuration File (LCONF) to define active execution nodes, hardware lines, and physical stations.

2. Perimeter Access Layer (Device Handlers)

  • Purpose: Translates device-specific message protocol formats into the system’s unified internal format.
  • ATM Device Handlers (ATMDH): Manage direct connectivity to automated teller machines, unpack specific vendor dialects (such as Diebold or NCR states), and track terminal hardware statuses.
  • POS Device Handlers (POSDH): Interface with point-of-sale acquirer terminals and merchants.
  • Security Operations: Triggers immediate payload encryption/decryption and Hardware Security Module (HSM) PIN-block translation directly within this ingestion ring.

3. Core Transaction Logic (Authorization System)

  • Purpose: Determines whether a payment request should be accepted, rejected, or modified.
  • Full On-Us Authorization: Inspects internal databases for matching account records, positive balances, and velocity thresholds to issue real-time decisions.
  • Parametric/Negative Checks: Validates card status against offline negative files, usage restrictions, or custom risk parameters.
  • Scripting Engine: Modern BASE24-eps variants execute localized transaction routing scripts via customized operators without forcing a compile rewrite of the core engine core.

4. Boundary Channels (Interchange & Host Interfaces)

  • Interchange Interfaces (ICH): Package and transform the transaction payload into international network profiles (e.g., Visa, Mastercard, regional switches). It handles strict message mapping and regional network check requirements.
  • Host Interfaces (HIF): Create synchronous links back to an institution’s underlying Core Banking system to apply ledger adjustments, check balances, or execute real-time holds.

5. Offline & Administrative Subsystems

  • Extract Component: Gathers active transaction logs and streams filtered payloads out to analytical reporting databases.
  • Refresh Component: Updates terminal operational data, key packages, and card exclusion lists from parent systems down to active execution nodes.
  • Settlement Initiator: Groups, cleanses, and batches net-clearing totals to finalize payment entries into regional clearinghouses.

Architectural Divergence: Classic vs. EPS

The structural design varies significantly depending on the generation of the software deployment:

BASE24 and BASE24-eps architecture overview
BASE24 and BASE24-eps architecture overview

End-to-End Component Transaction Flow

  1. An ATM transaction arrives at the network interface layer managed by XPNET.
  2. The message is routed to the Device Handler, which strips hardware packaging and requests translation from the HSM.
  3. The clean internal message passes to the Authorization Engine.
  4. If it is a “Not-On-Us” card, the engine identifies the destination BIN and transfers routing control to the Interchange Interface.
  5. The Interchange Interface maps the payload to the external scheme standard (such as Visa) and transmits it to the external network.
  6. The outbound network response is unwrapped by the Interchange component and tracked through the core engine to log final response codes.
  7. The transaction safely records inside the active log file, allowing the Extract / Settlement components to pick it up later during batch processing.

BASE24 and BASE24-eps architecture overview

BASE24 and BASE24-eps architecture overview
BASE24 and BASE24-eps architecture overview

HPE Nonstop Technology Architecture – specialized, 100% fault-tolerant infrastructure

The official HPE Nonstop Technology Architecture is a specialized, 100% fault-tolerant infrastructure built with a tightly integrated hardware and software stack designed to eliminate any single point of failure. Formal instruction and architectural frameworks have been modernized under the newly relaunched HPE Nonstop Compute Training Portfolio curriculum.

Originally developed by Tandem Computers in 1976, the platform eventually became part of Hewlett Packard Enterprise (HPE). Unlike standard servers that can crash due to a single component failure, NonStop uses a tightly integrated, “shared-nothing” architecture to ensure that if a hardware or software component fails, another instantly takes over with zero downtime or data loss.

Core Architectural Features

To understand how HPE NonStop works, you need to understand its unique design principles:

  • Shared-Nothing Architecture: Every processor has its own dedicated memory, I/O channels, and copy of the operating system. No single component is shared, eliminating any single point of failure.
  • Process Pairs: Applications run using a primary process and a backup process on a different processor. The primary process constantly copies its state to the backup. If the primary fails, the backup immediately takes over.
  • Massive Scalability: Systems can scale up seamlessly from small distributed environments to massive clusters containing up to 24,000 processor cores without interrupting running operations.
  • Hardware Platform: The modern software environment runs on industry-standard x86 architectures, available as physical server racks (like the HPE NonStop NS9 X5) or as virtualized instances in hybrid cloud environments.

Dual Operating Environments

HPE NonStop runs a specialized operating system called NonStop OS. Inside this OS, developers and administrators interact with two distinct environments:

  • Guardian Environment: The native, proprietary environment optimized for high-volume Online Transaction Processing (OLTP). It handles tasks sequentially through process-oriented manually-started jobs rather than traditional automated queues.
  • Open System Services (OSS): A UNIX-like, POSIX-compliant environment built on top of the NonStop kernel. This allows organizations to run standard open-source applications, tools, and scripts natively alongside Guardian.

Ecosystem and Use Cases

HPE NonStop is rarely used for standard office automation or basic web hosting. Instead, it serves as the backbone for global industries where an hour of downtime could cost millions of dollars:

  • Financial Transactions: Powers global stock exchanges, automated teller machines (ATMs), and retail point-of-sale credit card processing, eg. BASE24.
  • Travel and Logistics: Runs critical airline reservation systems and real-time cargo routing infrastructure.
  • Database Management: Features its own highly secure, distributed database engine called NonStop SQL, which guarantees absolute data integrity across all transactions.
  • Modern Development: Supports traditional languages like COBOL85 and ANSI C, alongside modern DevOps integrations like Git, Ansible, and Eclipse-based IDE environments.

If you plan to work directly with these systems, you can explore formal pathways like the Concepts and Facilities for HPE NonStop Systems course provided by HPE Education Services.


Core Architectural Layers (Diagram Blueprint)

An architectural blueprint of an HPE NonStop environment typically separates the layout into three core interdependent layers:

  • Hardware & Fabric Layer: Consists of independent, loosely-coupled Processor Nodes (handling up to 24,000 cores globally) connected via an ultra-fast InfiniBand or ServerNet system fabric backbone.
  • I/O & Subsystem Layer: Utilizes Cluster I/O Protocols (CLIMs), splitting tasks between Storage CLIMs (SCLIMs) and Network CLIMs (NCLIMs) to isolate external communication from main processing.
  • Operating System & DB Layer: Runs the NonStop OS, which simultaneously manages the traditional Guardian environment, Open System Services (OSS) for UNIX/Linux paradigms, and the NonStop SQL distributed database engine.

Recommended Architecture Training Curriculum

HPE organizes its technical blueprints into structured educational paths for engineers.

1. Foundational Blueprint Concepts

  • Course Code: U4147S (HPE Nonstop Compute System Fundamentals).
  • Focus: Delivers a top-down view of system goals, transaction processing, and fundamental architecture.
  • Key Modules: Explores Guardian vs OSS, Pathway application management, and basic database interaction.

2. System Operations & Administration

  • Course Code: H1SC3S (HPE Nonstop Compute System Administration I).
  • Focus: Maps physical and virtual components to real-world deployment.
  • Key Modules: Covers Processor Nodes, configuring SCLIMs/NCLIMs, and hands-on fault-scenario testing.

3. Low-Level OS Internals

  • Course Code: U8609S (HPE Integrity Nonstop Operating System Architecture).
  • Focus: Deep dive into runtime architecture, process control, and memory allocation.
  • Key Modules: Focuses on Inter-process Message Systems, synchronization mechanisms, and system debugging.

Training Delivery Options

Enrolling via HPE Education Services grants access to various professional development features:

  • HPE vLabs: Direct sandbox access to practice configuration and live fault injection inside virtual environments.
  • Digital Learner Credits: Flexible licensing options to assign corporate learning units across teams.
  • Modernized Tracks: Courses have been fully overhauled to support contemporary cloud paradigms and hybrid integration via HPE GreenLake frameworks.

My HPE NonStop (Tandem Computers) Certificates :

HPE NonStop (Tandem) Career Experience at Insider Technologies Limited, ITL
BASE24 eps monitoring

Mark Whitfield IT, Technical & Project Management Training Overview

Mark Whitfield, a Manchester-based Senior IT Project Manager, has completed extensive professional training throughout his career, focusing on project management methodologies, delivery software, and technical tools.

Core Project Management Methodologies :

  • PRINCE2 Practitioner: Certified as a registered PRINCE2 Practitioner in May 2011 via the ILX Group (Gold e-Learning).
  • Agile SCRUM Training: Attended in-house training with RADTAC in May 2011.
  • Advanced Engagement Management (Level 2): Completed at Capgemini in November 2017.
  • Project Management Fundamentals: Completed “Fundamentals of Successful Project Management” in February 2000 through Skillpath in Manchester.
  • Managing Multiple Projects: Attended “Managing Multiple Projects, Objectives and Deadlines” in October 1999/1998 via Skillpath.

Software & Cloud Platforms :

  • AZ-900 Microsoft Azure Fundamentals: Certified in February 2022.
  • Microsoft Project: Completed the Microsoft Project ’98 Certification Series in May 2000 through the IIL UK Education Centre in Reading.
  • Microsoft Excel Expert Skills: Upgraded skills via a 2017 Expert course and a July 2024 Udemy refresher.

Technical & Programming Courses :

  • Tandem / HP NonStop: Completed Tandem Guardian Principles (1993), Tandem Performance Analysis (1995), and Tandem TAL Programming (1995).
  • C / C++ Programming: Attended “C++ for Non-C Programmers” with Comtec Computer Training in March 1997.
  • Database Querying: Completed “Querying Microsoft SQL 2000 with Transact SQL” via QA Training in March 2009.
  • Web Applications: Attended “Developing MS ASP Web Applications using MS Visual Studio .NET” in January 2007.

Marketing & Communication Training :

  • Writing for the Web: Completed in May 2009 with gbdirect (iTrain Education in London).
  • Brochure & Document Design: Attended a SkillPath Seminar on designing marketing brochures and reports in April 2006.

Mark Whitfield is a Senior IT Project Manager based in Manchester

Mark Whitfield is a highly experienced Senior IT Project Manager based in Manchester, UK, with over 31 years of experience in the IT industry specializing in both Agile and Waterfall methodologies. He holds SC clearance (valid until 2031) and has a strong technical background in banking and digital project delivery, including experience as a developer in software development lifecycles (SDLC).

Mark Whitfield is a highly experienced Senior IT Project Manager based in Manchester
Mark Whitfield is a highly experienced Senior IT Project Manager based in Manchester

Professional Biography

After graduating in Computing in 1990, Mark began his career as a programmer specializing in Electronic Banking software on Tandem Mainframe Computers (HPE NonStop). He spent five years coding in COBOL85 and NonStop SQL for banking clients before transitioning into project management.

Mark has operated as a Senior IT Project Manager for over two decades, delivering complex projects for major blue-chip clients, including Jaguar Landrover, Heathrow, Royal Mail Group, and various financial institutions. He currently provides project management templates based on his extensive experience via his website, PROject Templates.

Example POaP Plan On a Page templates by Mark Whitfield

Key Skills & Expertise

  • Methodologies: Agile SCRUM, Waterfall, PRINCE2 Practitioner.
  • Technologies: HP NonStop (BASE24, TAL, C, C++, SQL), Java, .NET, Mobile (iOS, Android, Windows).
  • Areas: ATM software delivery, Gambling/Casinos, Public Sector/LRG, Payment Systems, Digital Transformation.
  • Clearance: SC Cleared until 2031.
Capgemini Engagement Manager, 2016 thru 2025
Capgemini Engagement Manager, 2016 thru 2025

Professional Career & Projects

Capgemini UK (Jan 2016 – Present)

  • Role: Client-facing SC Cleared Engagement Manager.
  • Projects: Delivered Waterfall and Agile digital projects for automotive, local regional government (LRG), postal services, and aerospace & defence sectors.
C&CA UK’s Communications & Engagement Award Winner 2022

Betfred (Late 2014 – Jan 2016)

  • Role: Senior IT Project Manager.
  • Projects: Managed mobile and online gambling/casino projects, including payment gateways, sportsbook, and virtual gaming using Agile SCRUM.

Wincor Nixdorf (Sept 2013 – Late 2014)

  • Role: Agile IT PM, Professional Services – Banking Division.
  • Projects: Managed ATM software delivery (Wincor Nixdorf work stream >£5M) for Lloyds Banking Group/Halifax.

Insider Technologies Limited (Aug 1995 – Sept 2013)

  • Role: Project Manager – Strategic Technical Initiatives.
  • Projects: Technical pre-sales, product management, and installation for HPE NonStop banking products (Reflex 80:20, RTLX).
HP NonStop TAL Programming Course
1995, HP NonStop TAL Programming Course

The Software Partnership / Deluxe Data (1990 – 1995)

  • Role: Programmer.
  • Projects: Developed code for sp/ARCHITECT-BANK on Tandem Computers for banks like TSB, Bank of Scotland, and Rabobank.

Professional Training & Certification

Registered PRINCE2 Practitioner (May 2011, ILX)
Registered PRINCE2 Practitioner (May 2011, ILX)
1990, BTEC HND in Computer Studies from Bolton Institute of Higher Education, BIHE
1990, BTEC HND in Computer Studies from Bolton Institute of Higher Education, BIHE